The present invention relates to a technique for lowering power consumption of a semiconductor integrated circuit device and, more particularly, to a technique effective to high-precision reduction of power consumption in a semiconductor integrated circuit device having a plurality of power supply regions in which low-power-consumption control is performed.
In recent years, a demand for lower power consumption is increasing. As a technique for reducing power consumption, for example, there is known a technique of dividing a core power region (for example, by logic blocks), controlling the on/off state of a power supply by the divided regions and, in the case of a low-speed operation or the like, controlling a power supply voltage VDD to reduce power consumption.
In the consumption power reducing technique, for example, an operating state of a semiconductor integrated circuit device is determined by a control of software, and on/off control on the core power region is controlled by a system controller or the like which controls the semiconductor integrated circuit device. The power supply voltage to be controlled is supplied from the outside of a semiconductor integrated circuit device.
In a technique of reducing power consumption in a semiconductor integrated circuit device of this kind, for example, a basic cell is used in which two low-threshold p-channel MOS transistors provided in the lateral direction and two low-threshold n-channel MOS transistors provided in the lateral direction are disposed in the vertical direction, a high-threshold p-channel MOS transistor is disposed on the upper side adjacent to the p-channel MOS transistors and a high-threshold n-channel MOS transistor is disposed on the lower side adjacent to the low-threshold n-channel MOS transistors (refer to, for example, patent document 1 (Japanese Patent Laid-open No. Hei 10 (1998)-125878).